Job Title: Principal Verification Engineer
Job Location: San Jose, CA or Allentown, PA
Job Salary: $160k - $200k + Bonus + Benefits + an incredible RSU package - $300k - $350k total comp
Requirements: Verification, UVM, System Verilog
We are a global tech leader in the semiconductor industry based in San Jose, California. We have been supplying cutting edge networking ASIC's and multi-chip solutions for the past 30 years. Due to growth we are seeking a Principal Verification Engineer who has 10+ years of experience with Verification, UVM, and System Verilog. Experience with RTL design and SERDES would be a huge plus but not a must have skill.
If you are a Principal Verification Engineer with UVM and System Verilog experience, please read on!
What You Need for this Position
Must Have Skills:
1.) 10+ years of experience as a Verification Engineer
2.) Experience with UVM
3.) Experience with System Verilog
4.) 7.) Bachelor's or Master's degree in Electrical Engineering, Computer Science or related
Nice to have skills:
1.) Experience with SERDES
2.) Experience with RTL design
What's In It for You
We are a global teach leader that values our employees, if hired, you will be rewarded with an offer that will include:
1.) $160k -$200k Salary + Bonus - $300k - $350k Total Comp
2.)Incredible RSU package
3.) 401k
4.) Benefits
5.) Work/Life Balance
So, if you are a Principal Verification Engineer with UVM and System Verilog experience, please apply today!
Applicants must be authorized to work in the U.S.
Gino Tunzi is recruiting for this position and the positions below.
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