Open to remote candidates in CA or NV only. Candidates onsite in Santa Clara or Las Vegas preferred.
Located in the South Bay Area, we are a Computer Hardware Manufacturing Startup that is disrupting the Data Center/HPC/AI markets by providing the world's first Universal Processor. We've raised over $40M in funding post Series B and are quickly growing!
We are looking for an RTL Design Engineer to help with our caches - this person will be working on a high performance L2 Cache unit serving the needs of state-of-the art AI processing elements!
Top Reasons to Work with Us
Join a startup, have an immediate impact!
Unlock the performance potential of nanometer-class chips!
Competitive Base, Equity, Full Benefits starting day 1, PTO, Relocation, 401K, and more!What You Need for this Position
BSEE or related
RTL Design experience
Understanding of high speed and low power processor pipeline designs / ASICs / SoCs and multi-core designs
Strong understanding of computer architecture
Experience with cache controller designs, understanding of cache coherency protocols, cache hierarchy
Logic design experience with state of the art deep submicron technologies specifically low power design techniques
Verilog / system Verilog / Synthesis / STA (Static timing analysis) / CDC / LINT
Knowledge of ARM and x86 and multicore processor designs is a plus
Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus..
So if you are an RTL Design Engineer w/ Cache experience, please apply today!
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Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Caroline Veillon
Applicants must be authorized to work in the U.S.
Email me to apply for this position