Located in Santa Clara, CA, we are a startup that is revolutionizing some of the most complex problems in big data analytics, deep learning, and large scale computing by creating the first universal processor.
With recent grants, $25M Series A, and a strong founding team, we are looking for an experienced Design Verification Engineer to execute projects using UVM based SOC verification. This person will be responsible for integrating 3rd party IP and working with protocols like PCIe, DDR4, Ethernet, etc...
We're interested in candidates who have 5-10 years of relevant UVM experience and are excited to take part in a fast paced startup operating in a dynamic, cross-functional environment.
Top Reasons to Work with Us
1. Join a startup, have immediate impact
2. Unlock the performance potential of nanometer-class chips
3. Competitive comp, potential equity, full benefits starting day 1, PTO and more!
What You Will Be Doing
Test plan development for block and chip; drive to close
Gate level simulation
Functional & code coverage
Assertions, cover properties & cover points
Bus Functional Model integration
Waveform debugging, RTL simulation
UVM tests and sequences
What You Need for this Position
Required:
- BS, MS or PhD
- 5-10 years UVM experience
- System Verilog
Preferred:
- RTL designs (flops, fifos Clock domain crossing)
- Protocols (PCIe, Ethernet, DDR4, etc)
- Create regression scripts for individual and batch jobs
..
If you have what we're looking for, apply now or email me at caroline.veillon@cybercoders.com !
Applicants must be authorized to work in the U.S.
Email me to apply for this position