Located in Santa Clara, CA, we are a startup that is revolutionizing some of the most complex problems in big data analytics, deep learning, and large-scale computing by creating the first universal processor!
With recent grants, $25M Series A, and a strong founding team, we are looking for an experienced Design Verification Engineer to execute projects using UVM based SOC verification. This person should have experience working on microprocessors, GPUs or other complex architectures and will be responsible for integrating 3rd party IP and working with protocols like PCIe, DDR4, Ethernet, etc...
We're interested in candidates who have 6+ years of relevant UVM experience and are excited to take part in a fast-paced startup operating in a dynamic, cross-functional environment.
We have multiple positions open at Mid, Senior, and Lead levels!!!
Top Reasons to Work with Us
1. Join a startup, have an immediate impact
2. Unlock the performance potential of nanometer-class chips
3. Competitive comp, equity, full benefits starting day 1, PTO, relocation to Bay Area, and more!
What You Will Be Doing
You'll be responsible for executing multiple UVM based verification projects, building constraints, waveform debugging, RTL + Gate-Level simulations, integrating Bus Function Models, and more.
What You Need for this Position
- BS/MS/PhD EE, CE or related
- 5+ years of UVM based SOC verification
- Processor Architecture
- System Verilog
BONUS:
- RTL design
- PCIe, DDR4/5, Ethernet (100G+)
..
So if you are a SOC Design Verification Engineer with microprocessors, GPUs, or other complex architecture experience, please apply today!
Applicants must be authorized to work in the U.S.
Email me to apply for this position