SOC Design Verification Engineer - ASIC, FPGA, Verilog, VHDL

Austin, TX • Santa Clara, CA • San Diego, CA • Dallas, TX • San Francisco, CA

Full-time $150,000.00 - $250,000.00

Posted 05/16/2023

If you are a SOC Design Verification Engineer with experience, please read on!
((THIS POSITION REQUIRES RELOCATION -- LOCATIONS MAY VARY, BUT OPPORTUNITIES IN WASHINGTON, BAY AREA AND AUSTIN)

Based in the Bay Area, we are an innovative company that collaborates with Fortune 100 companies on innovative new technology. This includes autonomous driving and AR/VR applications. Work with 3 of the top 100 companies in the world creating experimental technology that will revolutionize their respective industries.

What You Will Be Doing

- Working with 3 of the top 100 companies in the world
- Working with experimental tech that will revolutionize the future
- Work closely with Custom SoC department to provide great customer service to our clients and the projects at hand. Support, encourage and drive timely and accurate deliverables with customers within schedules
- Responsible for oversight and completion of debugging problems and troubleshooting in Real Time. This includes being responsible for Debugging Designs for High throughput, Low Latency of Pipeline and Dynamic Power Management at full system level.

What You Need for this Position

- Skills in ASIC / FPGA verification (directed test or SystemVerilog / UVM)
- Knowledge in design techniques Verilog or VHDL
- A good knowledge of simulation flow
- Good basis in scripting Python, Perl, Bash&

Prefered Skills:
- Masters Degree

What's In It for You

- Competitive Base Salary ($150k - $250k DOE)
- 20 days of PTO + 8 company holidays
- Medical
- Dental
- Vision
- 401k
- Generous 401(k) match

So, if you are a SOC Design Verification Engineer with experience, please apply today!

Applicants must be authorized to work in the U.S.

Additional ways to apply

Preferred Skills

Brandon Solano is recruiting for this position and the positions below.
Email me to apply for this position

Remote Principal Design Verification Engineer - UVM, sysverilog

San Francisco, CA•Redmond, WA•Austin, TX•New York, NY Full-time $160,000.00 - $225,000.00

Remote Design Verification Engineer - ASIC, UVM, System Verilog

San Francisco, CA•Redmond, WA•Austin, TX Full-time $160,000.00 - $225,000.00

Job ID: BS12-1698212

CyberCoders, Inc is proud to be an Equal Opportunity Employer

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.

Your Right to Work – In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.