If you are a Senior Design Verification Engineer with experience, please read on!
Job Title: Senior Design Verification Engineer
Job Location: Campbell, CA
Salary: $150,000-$180,000
Requirements: UVM, AMBA AXI, Verilog
Top Reasons to Work with Us
1. Based in Campbell, we are a semiconductor company.
2. Our company has been around for over a decade, so we offer a unique balance of stability and a small, tight-knit feel.
3. You will have the chance to lead new development projects with a talented team.
What You Will Be Doing
- Advanced UVM based test bench development and debugging
- Defining, documenting, developing and executing RTL verification test/coverage at system level
- Performance verification and power-aware verification
- Triaging Regressions, Debugging RTL designs in Verilog and SystemVerilog
- Help improve and refine verification process, methodology, and metrics
- UVM expertise on complex SoC projects from test bench development to verification closure
What You Need for this Position
- 8 or more years of design and verification experience and a plus in interconnect verification experience
- Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
- Strong RTL (Verilog) and UVM/C test bench debugging skills
- Experience integrating vendor provided VIPs for unit and system level verification
- Experience with Arm AMBA protocols
- This opportunity involves high performance, low power designs on a highly visible project
What's In It for You
- Competitive salary
- RSU's
- Full Benefits
- 401k
- PTO
- Holidays
- Great Place to Work
So, if you are a Senior Design Verification Engineer with experience, please apply today!
Applicants must be authorized to work in the U.S.
Email me to apply for this position