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Design Verification Engineer - System Verilog, SoC

Santa Clara, CA

Compensation Unspecified

Posted 02/05/2020

Located in Santa Clara, CA, we are a startup that is revolutionizing some of the most complex problems in big data analytics, deep learning, and large scale computing by creating the first universal p...

SoC Verification
System Verilog
UVM Sequence / Phases / Callback
Waveform Debugging / RTL Simulation
3rd Party Bus Functional Model Integration

Junior ASIC Verification Engineer

Milpitas, CA

Full-time $100k - $130k

Posted 01/31/2020

If you are a Junior ASIC Verification Engineer with experience, please read on! We are an innovative, software company located near San Francisco looking to add on multiple Engineers to our team! Our...

C
SOC
Unit
Sub-System
System Verilog