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Design Verification Engineer - System Verilog, SoC

Santa Clara, CA

Compensation Unspecified

Posted 10/03/2019

Located in Santa Clara, CA, we are a startup that is revolutionizing some of the most complex problems in big data analytics, deep learning, and large scale computing by creating the first universal p...

SoC Verification
System Verilog
UVM Sequence / Phases / Callback
Waveform Debugging / RTL Simulation
3rd Party Bus Functional Model Integration