Sr. Pre-Silicon Verification Engineer

1) Competitive Compensation ($150K - $200K+ base depending on experience)
2) Comprehensive Benefits Package including sign-on bonus and relocation assistance!
3) The chance to join a global leader in the analog/power integrated circuit industry!

The Digital Verification Engineer will be leading verification development infrastructure for complex digital ASICs including tasks to create, maintain and drive verification plan/testcase development. Responsibilities include:

- UVM and System Verilog based Digital Verification environment definition and development.
- Real number modeling of analog circuits to facilitate DMS(Digital-Mixed Signal) functional testing
- Experienced in modeling with Verilog-AMS
- Verification IP (VIP) standardization, definition, development and documentation.
- Define VIP's integration into the Project's Digital Verification environment.
- Digital Verification Metrics definition for RTL and Gate-Level Verification.
- Test Plan definition and development.
- Digital Verification Automation and Scripting.
- Regression's infrastructure definition, development and management.
- Close interaction with Senior Digital and Analog Designers to develop test-plan and/or VIP models.
- Lead and/or assist with digital verification Tasks of multiple projects.
- Review Digital Verification Metrics and Results of multiple projects.
- Define and design Digital Verification Top-Level Tests.
- Analyze and debug test results, code coverage and functional coverage.
- Digital Verification estimation, planning and scheduling to meet tape-out dates.

BS (MS or PhD preferred) degree in Electrical Engineering or equivalent with 5+ years experience in the following:

- Digital Verification (UVM, System Verilog)
- RTL and Gate-Level Verification
- Design Verification skills and areas: Constraint random tests, SV assertions, coverage metrics, analog and digital DV modelling, DV test plans, regression analysis and reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.
- Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation and Simulation, AMS Sims, etc.
- Knowledge & Use of industry standard ASIC tools/flow for daily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.
- Excellent scripting and automation skills using TCL, Python or C/C++.

Preferred:

- Knowledge of power management industry/applications
- I2C, I3C, SPI, USB, PMBUS
- Embedded designs and/or firmware development
- GITLab, SVN, or equivalent version control