If you are a Lead ASIC Physical Design Engineer with experience, please read on!
Job Title: Lead ASIC Physical Design Engineer
Job Location: San Jose, CA
Compensation: $150K - $225K base Depending on experience plus stock options
We are a small 20-person Smart Interconnect technology company focused on enabling efficient and performant composable architectures to enable flexible, scalable, low latency composable systems. We provide silicon, hardware, and software which leverages the Compute Express Link (CXL) interconnect standard to provide high-performance connectivity to a broad ecosystem of components. We are a next-generation infrastructure company addressing a $500 billion dollar market composed of on-prem, edge data center, and core data center equipment. We recently raised $17 million in a Pre-Series A round and are now rapidly expanding.
Top Reasons to Work with Us
1) Competitive Compensation ($150K - $225K base Depending on Experience)
2) Comprehensive Benefits package including stock options!
3) The chance to join a small start-up tackling challenging problems with huge upside potential!
What You Will Be Doing
- Physical design engineer supporting the full chip creation, layout and final delivery of GDS-2.
- Work with ASIC vendor to drive them for timing closure/STA, layout, RAS features and on chip repair methodology for the best solution in the chip industry.
- Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability (DFT), floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
- Resolve design and flow issues related to physical design, identify potential solutions, and drive execution.
- Deliver multiple ASICs with physical design of an end-to-end integration of ASIC/SoC design.
What You Need for this Position
Must have a BSEE / MSEE or similar degree with 10-15+ years experience with the following:
- ASIC Physical Design
- RTL to GDSII flow and design tapeouts in 7nm or below process technologies
- Experience taking multiple ASICs from inception to final delivery in production
- Low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
- EDA tools like DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus or Calibre.
- Running Physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs.
- Static timing analysis (STA) and concepts, defining timing constraints and exceptions, corners/voltage definitions.
- Block-level and Full-chip floor-planning and power grid planning.
- Custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
- Python, TCL, Perl programming.
So, if you are a Lead ASIC Physical Design Engineer with experience, please apply today! or send an updated copy of your resume to Mike.Vandenbergh@CyberCoders.com for immediate consideration!
Applicants must be authorized to work in the U.S.
Email me to apply for this position