If you are a Package Design Engineer - Signal Integrity -Power Integrity with experience, please read on!
((THIS POSITION IS BASED IN MILPITAS - 3 DAYS IN OFFICE - Sign on Bonus Available to help with relocation))
Our company is world renowned when it comes to with our partnerships with FAANG corporations. We hold many patents and produce some of the highest end SOC products on the market.
Top Reasons to Work with Us
We have 12-20% bonus yearly - we also pay 100% of medical dental vision insurance and are closed the week of 4th of July and Christmas and a additional 3 weeks of PTO. 6 % match on 401K . In office 3 days a week at home 2 days a week.
What You Will Be Doing
" DDR frequency and time domains model and jitter analyses and path findings to improve package and PCB layout and improve high-speed interconnections
" Clock jitter analyses, routing, clock tree analyses
" Simulating multi-physics electro-thermal analysis
" Collateral packaging manufacturing and assembly rules
" Hands on package design; high-speed SI and PI, die and package decoupling caps optimizations, package and PCB SI and PI Characterizations, impedance verification, high frequency s-parameters extraction, Hspice model, package Hspice and RLC model extraction and designs
" Hands on high-speed package and PCB design: high-speed Serdes 112 Gbps, PCIeX5 and 6, LPDDR4,5, Ethernet 25 GBps, power aware SI/PI analysis, up to 40 GHZ s-parameters extraction and verification
What You Need for this Position
" 8 to 10 years of experience in semiconductor packaging design, modeling, and simulations
" Record of success in cross-functional team environment
" Good experience with SI/PI tools for package level extraction/simulation
" Ability to work with Package Layout engineers
" Strong presentation and communication skills
" Time domain analyses and jitter budgeting for PCIe2/3/4/5, Serdes 112 GBps, Ethernet 25 Gbps, LPDDR4/5X MIPI, high-speed frequency signaling
What's In It for You
- Competitive Base Salary $160,000 - $215,000 (DOE)
- 100% paid Health / Dental / VIsion
- 3 weeks PTO ( with the week of July 4th and December to New Years off)
- 6% 401k Match
- 3 days in office two days at home
So, if you are a Package Design Engineer - Signal Integrity -Power Integrity with experience, please apply today!
Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Brandon Solano
Applicants must be authorized to work in the U.S.