Work on fantastic projects,100 % fully remote now and permanently!
Accepting mid-level to principal level candidates!
Fantastic salaries & quick interview process!
What You Will Be Doing
Job Title: Design Verification Engineer of SOC
Skills in ASIC / FPGA verification (directed test or SystemVerilog / UVM)
Basic knowledge in design techniques Verilog or VHDL
Good knowledge of simulation flow
Good basis in scripting Python, Perl, Bash&
A good level in English, both writing and oral skills
Humanly, you have to be rigorous and have a good analytical mind, you have to enjoy working in a team and being diplomatic, in particular when you have to point out the bugs discovered.
What You Need for this Position
- System Verilog
- UVM
- VHDL
- Verification Engineer
- FPGA
- FPGA Verification
- ASIC
- Perl
- Bash
What's In It for You
- Vacation/PTO
- Medical
- Dental
- Vision
- 401k
Benefits
- Vacation/PTO
- Medical
- Dental
- Vision
- 401k
So, if you are a FULLY REMOTE- SR. Verification Engineer-System Verilog UVM with experience, please apply today!
Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Maria Reyes
This job is open to telecommute candidates.
Applicants must be authorized to work in the U.S.
Email me to apply for this position