If you are a FULLY REMOTE SOC Design Verification Engineer - SystemVerilogUVM with experience, please read on!
Based in the Bay Area, we are an innovative company that collaborates with Fortune 100 companies on innovative new technology. This includes autonomous driving and AR/VR applications and more!
***THIS ROLE IS FULLY REMOTE AND CAN BE WORKED FROM HOME***
Top Reasons to Work with Us
***THIS ROLE IS FULLY REMOTE AND CAN BE WORKED FROM HOME***
What You Will Be Doing
***THIS ROLE IS FULLY REMOTE AND CAN BE WORKED FROM HOME***
What You Need for this Position
***THIS ROLE IS FULLY REMOTE AND CAN BE WORKED FROM HOME***
4+ years of experience with:
System Verilog UVM
Skills in ASIC / FPGA verification (directed test or SystemVerilog / UVM)
Knowledge in design techniques Verilog or VHDL
A good knowledge of simulation flow
Good basis in scripting Python, Perl, Bash&
- Design Verification
- UVM
- Design Verification Engineer
- DV
- System Verilog
- SystemVerilog
- System Verilog UVM
- SystemVerilog UVM
What's In It for You
***THIS ROLE IS FULLY REMOTE AND CAN BE WORKED FROM HOME***
***THIS ROLE IS FULLY REMOTE AND CAN BE WORKED FROM HOME***
So, if you are a FULLY REMOTE Design Verification Engineer with experience, please apply today!
Applicants must be authorized to work in the U.S.
Email me to apply for this position