If you are a FPGA Design Engineer- RTL Development-System Verilog with experience, please read on!
We are a system on a chip company formed in March 2015 we have about 2,500 employees worldwide, our U.S headquarters is located in Milpitas California. We have an extensive lineup of IPs that power SoCs for a range of applications, including automotive, data center & network, and smart devices.
What You Will Be Doing
If you are a FPGA Design Engineer- RTL Development-System Verilog with experience, please read on!
Develop FPGA designs and subsystems (involving ASICs), from concept to product including:
" Work Closely and collaborate with functional teams to provide working FPGA Prototype and emulation platforms.
" Design, document, implement ASICs on Prototyping/emulation platforms.
" Work closely with hardware team (Arch, design verification etc.) and firmware team to bring up new SoC Designs and platforms.
" Completing implementation in RTL, RTL/netlist verification and evaluating FPGA (e.g. Xilinxs Vivado, HAPS etc) synthesis and P&R results for performance and cost
" Ensuring robust and complete timing constraints and evaluating STA results.
" Balancing performance, area, power, complexity and timing
" Determining and executing development, integration, bring-up and test plans.
" Contribute during every phase of SOC Designs from concept to production (e.g. Arch, design, Interfacing with third-party IP/vendors, verification, firmware development, ECOs, Silicon bring up etc.)
What You Need for this Position
" BS or MS in Electrical Engineering.
" 5+ years of FPGA design experience.
" 5+ years of RTL Development using Verilog, System Verilog, VHDL
" Demonstrated experience working on FPGA Design projects, including work with SOC (ARM/RISC-V CPU based, NoC), MIPI, XAUI, USB, Flash, SDIO, PCI-E, and DDR# Interfaces.
" Familiarity with Synopsys(HAPS, Proto-compiler) and Xilinx tools/IPs for FPGA Design and implementation.
" Strong coding, debugging skills on both UVM and FPGA Platforms
" Experience with Low Speed peripherals like SPI, UART, I2C. I2S, CAN, WDTs, GPIO etc.
" Hands on experience with Debuggers like JTAG IDE (Lauterbach, J-Link, ARM-DS, Keil etc.) and Testers & Scope.
" Proven expertise in one or more of the following domains: CoreSight, SoC-400, SoC-600, OCP, AXI, ACE, AHB and APB
" Familiarity with revision control concepts and tools (e.g. Subversion)
" Experience with Perl, Tcl, Python, Unix scripting.
Preferred qualifications:
" Experience with Hi-Speed Interfaces like MIPI, PCIe, USB 3.1, UFS, LPDDR4/5 etc. is a plus.
" Experience with Protium FPGA platform is a plus.
" Experience with Zebu or Palladium emulation platforms is a plus.
" Experience with multi FPGA implementation, partitioning, Secure boot, OTP/SRAM testing etc.
" Good knowledge of embedded camera system and CMOS imaging sensor devices.
" Familiarity with MIPI C /D PHY & have Prior experience with Image Sensors & be able to Tune & bring up different Types of Sensors.
What's In It for You
- Competitive Base Salary: $180,000 - $250,000 (DOE)
- Premium Health/Dental/Vision insurance
-12-20% bonus yearly
- Closed the week of 4th of July and Christmas with an additional 3 weeks of PTO.
- 6 % match on 401k
- Hybrid Schedule office 3 days a week at home 2 days a week.
So, if you are a FPGA Design Engineer- RTL Development-System Verilog with experience, please apply today!
Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Brandon Solano
Applicants must be authorized to work in the U.S.
Email me to apply for this position