We are a rapidly growing leader with a global presence, working on the most cutting-edge iOT & 5G SOC technology on the market!
We have a vibrant, up-beat startup environment where you'll be exposed to the latest tech with tons of room for growth. You will have the chance to shine as the leader of all things digital and rise the ranks as we continue to scale out our products with some of the best-known consumer partners in the biz. As a Senior Level Verification engineer (Staff, Sr. Staff, Principal, Lead) in our org., you will have a huge impact on shipping current & future chips successfully. There may not be a better available opportunity in the area right now for a senior ASIC design Verification engineer to come in, make an impact on our products shipping and eventually cash out when we exit!
What You Will Be Doing
- Add hands-on value to our digital verification (ASIC Verification) processes & hands on verification of our chips
- Using SystemVerilog & utilizing UVM to verify our chips
- F2B Verification
- Contribute to resource planning and scheduling
- Define key components of digital/system design as well as test strategies, flows and implementation methodologies
- Work on debugging when needed in a timely fashion
- Work with various teams (System, Software, RF, Analog, Test) and provide support when needed.
What You Need for this Position
- Outstanding fundamentals & hands on experience with SystemVerilog & UVM (or related Methodology)
- Various Verification tool experience
- Ability to adapt to changing requirements on various projects
- Specific Cadence F2B design tool experience is helpful
- Wireless chip verification or related communications product experience is a plus
- Strong understanding of Mixed Signal concepts
- Strong experience with highly integrated Mixed Signal SoCs with successful commercial release
- Embedded systems, wireless protocols, signal processing, power management, and digital interfaces
- Verilog / System Verilog
- Embedded programming languaes including C / C++ / Perl / TcI / Python
What's In It for You
- Top pay, benefits (health, dental, 401k, PTO)
- Equity in a company with a ton of liquidity upside potential
- Opportunity to get out of a big company or away from boring technology to build the latest 5G products
So, if you are a Senior (Staff, Sr. Staff, Principal, Lead, etc.) design verification engineer with outstanding SystemVerilog & UVM experience, please apply today!
This job is open to telecommute candidates.
Applicants must be authorized to work in the U.S.
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